Vaire Computing is developing Near-Zero Energy Chips to unlock the future of computing. As Moore’s Law slows and AI demand accelerates, conventional architectures are constrained by unsustainable energy and thermal limits. Reversible Computing provides a rare breakthrough: a way to decouple energy use from compute growth, enabling the hardware required for the machine intelligence era.

This session introduces Vaire’s approach and core technology, presents results from the first test chip fabricated in standard CMOS, and outlines the technical findings that validate energy recovery at the logic level. The discussion highlights two implications: co-designed IP to overcome thermal bottlenecks in custom ASICs, and system-level deployment to improve tokens-per-joule and total cost of ownership.

The talk concludes with the scaling law behind the technology and the roadmap toward production silicon later this decade. Early silicon results demonstrate that energy recovery is achievable in standard processes today, establishing the foundation for a new class of compute architectures capable of sustaining AI’s growth.

Generative AI is fundamentally changing how datacenters are built, putting three types of silicon center-stage: GPUs, custom AI ASICs, and advanced networking processors. Driven by these technologies, the datacenter processor market soared to $147 billion in 2024 and is expected to double by 2030, largely thanks to explosive growth in GPUs and specialized AI ASICs.

While GPUs remain the reference for AI training and inference, hyperscale providers, eager to reduce their dependence on Nvidia, are increasingly co-designing specialized AI ASICs with chipmakers like Broadcom, Marvell, and Alchip. These ASICs sacrifice some versatility to achieve superior performance and energy efficiency, creating opportunities for a thriving startup scene featuring companies like Groq, Cerebras, and Tenstorrent, and spurring major waves of venture investment and mergers. Crucially, chiplet architectures, which combine multiple smaller chip components into a single, optimized package, are now key to driving GPU and ASIC performance upward, beyond what traditional single-chip designs can deliver.

As AI models become ever larger and require responses within milliseconds, networking silicon has become just as critical as processors themselves. DPUs, smart network cards, and advanced switches now coordinate massive arrays of accelerators, making both scale-up and scale-out networks a pivotal part of datacenter performance.

Ultra Ethernet is a suite of technologies designed to enhance Ethernet for use in AI and HPC.  This talk will describe the motivation for and goals of the Ultra Ethernet Consortium, discuss the AI and HPC problems that it addresses, and go into some technical details of the Ultra Ethernet 1.0 solution, including Ultra Ethernet Transport -- the high-performance transport protocol designed by UEC specifically to support AI and HPC.

This demo will showcase how Innodisk’s AccelBrain AI software stack powers on‑premise, private large language model (LLM) deployment and then extends those capabilities to the edge. We’ll show how AccelBrain seamlessly integrates with our APEX-E100 and APEX-P200 platforms, enabling efficient, secure, and real‑time AI processing at the edge—without relying on the cloud.

Scaling AI accelerators only happens with extreme density and high-speed performance interconnects. Samtec’s Si-Fly® HD co-packaged interconnect systems provide the highest density 224 Gbps PAM4 solution in today's market. Electrically pluggable co-packaged copper and optics solutions (known as CPX) adjacent to AI accelerators are achievable on a 95 mm x 95 mm or smaller substrates. This proximity eliminates long PCB traces, greatly reducing loss while preserving serviceability in a pluggable form factor.

In the Demo Stage presentation, Samtec technical experts will summarize real-world performance data of CPX implementations in various 224 Gbps PAM4 signal channels typically found in AI acceleration platforms. Additionally, an preview of AI scale-up and scale-out networks using CPX technologies will also be presented.